The performance of server systems has been limited by the low bandwidth associated with I/O subsystems. Attempts to improve this performance bottleneck have been geared towards increasing the I/O bandwidth. However this causes an increase in the number of I/O interrupts received by the server. The increased number of I/O interrupts unnecessarily consumes the server's time thereby degrading the overall performance of the server.
To overcome this bottleneck, a separate I/O processor or controller is typically used to perform the tasks that would normally be performed by the server to handle I/O processing. The use of an I/O controller reduces the overhead incurred by the server to process the I/O interrupts and related I/O processing tasks thereby increasing I/O throughput and improving the performance of the server. For these reasons, most server systems utilize an I/O controller to interface between external peripheral devices and the server.
FIG. 1 illustrates an exemplary computer system 100 utilizing an I/O controller 102. There is shown an I/O controller 102 connected to a primary peripheral component interconnect (PCI) bus 104 and to external I/O devices 106 through a small computer system interface (SCSI) channel 108. The I/O controller 102 includes a secondary PCI bus 110 to which is connected a processor 112, a memory controller 114, a SCSI controller 116, and a PCI-to-PCI bridge 118. The PCI-to-PCI bridge 118 connects the devices coupled to the secondary PCI bus 110 with the devices connected to the primary PCI bus 104. A host central processing unit (CPU) (not shown) is in communication with the primary PCI bus 104. The memory controller 114 is connected to an external memory device 120.
The processor 112 is dedicated to handling I/O requests received from the host CPU. These I/O requests can be to access data from one of the external I/O devices 106. The SCSI controller 116 interfaces with the external I/O devices 106 to transmit and retrieve data to and from these devices 106. The memory 120 is used as a temporary storage area to store data that is in transit between the host CPU and the external I/O devices 106. For instance, data that is written onto an external I/O device 106 is stored in the memory 120 so that it can be encoded with parity bytes prior to storage. Likewise, data that is read from an external I/O device 106 is stored in the memory 120 so that it can be decoded before it is transmitted to the host CPU.
A drawback with the design of this particular I/O controller 102 is that it is not fault tolerant. In the event the memory 120 fails, all I/O activity ceases. Such a memory failure is apparent when an intolerable number of parity errors is detected. Since the I/O controller 102 does not have a redundant memory, all I/O activity ceases thereby severely degrading the performance of the computer system 100. Accordingly, there exists a need for a reliable I/O controller that can accommodate memory failures.